Junior Engineer/Engineer - RTL Design and Synthesis

Experience Level : 1–3 Years

Employment Type: Full-Time

Key Responsibilities:

· Design, develop, and verify Register Transfer Level (RTL) modules for digital hardware.

· Perform logic synthesis, timing checks, and optimizations using Xilinx Vivado.

· Simulate and debug RTL functionality using Icarus HDL (iverilog) or equivalent tools.

· Collaborate with verification engineers to resolve functional and timing issues.

· Document design specifications and support block/system-level integration.

Required Skills & Qualifications:

· Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or related field.

· 1–3 years of hands-on experience in RTL design using Verilog/VHDL/SystemVerilog.

· Solid understanding of digital design fundamentals (combinational/sequential logic, FSMs, pipelining, clocking, resets).

· Experience with Xilinx Vivado (synthesis, implementation, timing analysis).

· Experience with Icarus HDL (iverilog) or other RTL simulation tools.

· Familiarity with version control systems (e.g., Git) and basic Linux shell usage.

· Strong analytical, debugging, and problem-solving skills.

Nice to Have (Optional) :

· Exposure to FPGA-based prototyping and bitstream generation.

· Knowledge of scripting languages (TCL, Python, or Shell) for design automation.

· Understanding of low-power design techniques and constraints.

· Experience with industry-standard verification methodologies (UVM, functional coverage, assertions).

Job Location: Dhaka 

Salary: Negotiable  

Compensation & Other Benefits : Mobile bill, Medical allowance, Provident fund, Weekly 2 holidays, Insurance, Gratuity    

Lunch Facilities: Partially Subsidized

Salary Review : Yearly  

Festival Bonus: 2 (Yearly) 